`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:59:31 10/04/2011
// Design Name:   RAM
// Module Name:   C:/Users/david/Desktop/16bitcpu/RAMTEST.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RAM
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RAMTEST;

	// Inputs
	reg [15:0] DI;
	wire [1:0] DOP;
	reg [9:0] ADDR;
	reg CLK;
	reg RESET;
	reg WE;
	reg EN;

	// Outputs
	wire [15:0] DO;

	// Instantiate the Unit Under Test (UUT)
	RAM uut (
		.DI(DI), 
		.DO(DO), 
		.DOP(DOP), 
		.ADDR(ADDR), 
		.CLK(CLK), 
		.RESET(RESET), 
		.WE(WE), 
		.EN(EN)
	);

	initial begin
		// Initialize Inputs
		DI = 0;
		ADDR = 0;
		CLK = 0;
		RESET = 0;
		WE = 0;
		EN = 0;

		// Wait 100 ns for global reset to finish
		#100;
		
		// Add stimulus here
		RESET=1;
		#30
		RESET=0;
		
		
	end
      
		always begin
		#5 CLK=~CLK;
		end
		
endmodule

